1. Technical Field
The present invention relates generally to integrated circuits, and more particularly, but not exclusively, to silicon photonic structures to interconnect integrated circuit chips.
2. Background Art
A continuing focus of the microelectronics industry is the enablement of computer chips (also referred to as dies) having greater density, higher performance, and lower cost. As part of this effort, microelectronic packages containing multiple dies have been developed. Such multi-chip packages (MCPs) offer the potential for increased architectural flexibility at reduced cost but to do so must provide appropriate die-to-die interconnect densities in a way that is cost-effective. The interconnect density is an important consideration because an insufficient number of die connections would limit the bandwidth capability for the affected die interface, and thus logic-logic and/or logic-memory communications would suffer.
Existing interconnect architectures, such as those of on-package input/output (OPIO), use copper or other conductors as the transmission media for communication between two integrated circuit (IC) chips. These electrical interconnects are subject to loss and crosstalk degradation, especially when implemented in high density form factors. As successive generations of IC chips continue to scale in size and speed, existing chip interconnect technologies are reaching interconnect density limits, signaling rate limits and other design and operational constraints imposed by the use of electrical interconnects.